Low power consumption, fast operation, and high precision are required of analog-digital converters (hereafter ADCs). In order to achieve fast operation with low power consumption, a time interleave design is advantageous, in which a plurality of (M) ADC units are arranged in parallel, and the plurality of ADC units perform time-division conversion, in order, of input analog signals into digital signals. In such an ADC with a time-interleave design, the sampling frequency of each ADC unit is, relative to the sampling frequency f of the ADC, reduced to the frequency f-M, and power consumption may be reduced, while the overall sampling frequency may be raised.
On the other hand, in the case of a time interleave ADC, there is the problem that mismatches between characteristics of the plurality of ADC units arranged in parallel may cause unwanted waves or errors (spurious components), so that the AD conversion characteristic is degraded. Mismatches in the characteristics of ADC units include the offset (shift between input and output) and shifts in the gain (slope of the output relative to the input) of the ADC units, and may also include shifts in the timing of switching of the plurality of ADC units. Hence mismatches between the characteristics of the plurality of ADC units are suppressed.
Vigorous development efforts are in progress to correct offset errors and gain errors among such mismatches in characteristics. As one such effort, digital background correction has been proposed, as described for example in Non-patent References 1 and 2.
In particular, in Non-patent Reference 2, the above-described time interleave type ADC is described. And, in Non-patent Reference 2, a configuration for digital background correction of offset errors is described in which an input analog signal is multiplied by a pseudorandom binary signal to perform spreading; the offset component of DC component is removed from this AD-converted signal, which is again multiplied by a pseudorandom binary signal to perform despreading. By means of this configuration, offset components in each of the ADC units are removed, so that such a configuration is suitable for time interleave designs.                Non-patent Reference 1: “A 2.5 V 12 b 54M sample-s 0.25 μm ADC in 1-mm2 with Mixed-Signal Chopping and Calibration”, Hendrik van der Ploeg, IEEE Journal of Solid-State Circuits, Vol. 36, No. 12, December 2001.        Non-patent Reference 2: “A 10 b 120M sample-s Time-Interleaved Analog-to-Digital Converter with Digital Background Calibration”, Shafiq M. Jamal, IEEE Journal of Solid-State Circuits, Vol. 37, No. 12, December 2002.        
In the configuration described in Non-patent Reference 2 above in which digital background correction of offset errors is performed, a spreader to multiply the input analog signals by pseudorandom binary signals is necessary. This spreader normally is realized by a plurality of transistor switches; but the existence of transistor switches has the harmful effect of causing distortion of analog signals. That is, because the turn-on resistance of transistor switches fluctuates with the input analog signal level, distortion occurs in the analog signals output from switches.